Power7


Timothy Prickett Morgan  разместил статью на джунглях с некоторыми подробностями о новых процессорах.

Up until now, about the only thing anyone knew about the Power7 chip is that it was being implemented in a 45 nanometer process and, thanks to confirmation from Ross Mauri, general manager of the Power Systems division last year, it would have eight processor cores.

Today, Handy said that the Power7 chip, in fact, would come with variants that have four, six, or eight cores and that each core would have as many as four processor threads per core. So a single Power7 chip could have as many as 32 different processor threads, compared to four threads with the Power5 through Power6+ generations of chips. (The Power4 and Power4+ chips did not support simultaneous multithreading, but were the first chips in the world to have two cores on a die.) IBM has not said how far it will scale its Power7 servers, but if it does 32 sockets as it does today with the Power 595 (and given the statement above about upgrade paths, this stands to reason), then a future 595-class box will be able to support 256 processor cores and 1,024 threads.

That large thread count is one of the reasons why IBM will officially support up to 1,000 logical partitions per Power7 system, up from the maximum of 254 with Power5 through Power6 machinery. IBM techies told me ahead of the Power6 launch that the chip was able to support over 1,000 partitions, but Big Blue did not allow that many to run because of processor capacity limitations.

The Power7 chips will have on-chip DDR3 main memory controllers, and the faster memory speeds will help get processors and main memory back closer together if IBM keeps the clock speeds of the Power7 chips between 3 GHz and 4 GHz, as expected. Current DDR3 memory runs at 1.07 GHz and 1.33 GHz, and will soon be running at 1.66 GHz. The DDR2 main memory used in Power5 through Power6+ iron runs at 400 MHz, 533 MHz, 667 MHz, and 800 MHz. That’s arguably too slow for a processor that is getting close to 5 GHz in clock speed or just hitting it, as the Power6 and Power6+ chips do, depending on the server.

Two more things.

One: When the Power Systems division was created out of the converged System i and System p product lines back in 2007, IBM said that it was looking at bringing Live Partition Mobility to the i5/OS platform, not just keep it on the AIX platform. Live Partition Mobility, and its companion Workload Partitions (WPARs) or Live Application Mobility, would be very useful features for a Power6-to-Power7 upgrade. AIX shops will learn this, but i shops won’t. AIX customers who want to move to Power7 machines will be able to take an extra box they have and move their running workloads off a box they want to upgrade using Live Partition Mobility, then power it down, add the Power7 books, put on the patched AIX 6.1, and move the workloads back onto LPARs running on the Power7 box. The i shops that want to move to Power7 boxes are going to have to do it the old-fashioned way by either having a high availability cluster of production and backup machines, upgrading on half of the cluster at a time, or do a backup, upgrade, restore three-step.

Two: AIX 6.1 and i 6.1 will get patches to support the Power7 chips, and then AIX 7 and i 7 will follow the new Power7 iron to market (presumably with lots of new software features) about 90 days or so later.

Полный текст статьи: http://www.itjungle.com/bns/bns072109-story01.html

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